`include "C:\Users\lenovo\Desktop\Files\Linear_RISCV\LR_ver_0\src\include\include.vh"
module 	lsu(
    input				    clk,
    input                 rst_n,

    input  [63:0]       exu_out,
    input  [63:0]    Store_data,
    input  [2: 0]  Load_sel_lsu,
    
    input  [3:0]       exe_type,
    input  [2: 0]  ctrl_bus_lsu,
    
    output [63:0]     Load_data,
    output [63:0]        Rd_lsu,
    output           WB_sel_lsu,
    
    output            Reg_W_lsu
);  wire    Reg_W;
    wire    Mem_W;
    wire    Mem_R;
    wire   [63:0]      Dmem_Addr;
    wire   [63:0]      Dmem_R_Data;
    assign Reg_W=ctrl_bus_lsu[2];
    assign Mem_W=ctrl_bus_lsu[1];
    assign Mem_R=ctrl_bus_lsu[0];
    assign Rd_lsu=exu_out;
    assign Reg_W_lsu=Reg_W;
    
    assign WB_sel_lsu = (exe_type == `EXE_TYPE_LOAD);
    
    DMEM_u DMEM_inst(
        .clk(clk),
        .rst_n(rst_n),
        .Mem_W(Mem_W),
        .Mem_R(Mem_R),
        .Dmem_Addr(Dmem_Addr),
        .Dmem_W_Data(Store_data),
        .Dmem_R_Data(Dmem_R_Data)
    );
    DMEM_ctrl DMEM_ctrl_inst(
        .Load_sel_exu(Load_sel_lsu),
        .exu_high(exu_out[10:0]),
        .Dmem_R_Data(Dmem_R_Data),
        .Dmem_Addr(Dmem_Addr),
        .Load_data(Load_data)
    );
    

endmodule


